View IDT7204L20DG_4561101.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 dsc-2661/16 ? 2008 integrated device technology, inc. all rights reserved. product subject to change without notice. october 2008 cmos asynchronous fifo 2,048 x 9, 4,096 x 9 8,192 x 9, 16,384 x 9 32,768 x 9 and 65,536 x 9 idt7203 idt7204 idt7205 idt7206 idt7207 idt7208 idt and the idt logo are registered trademarks of integrated device technology, inc. commercial, military and industrial temperature ranges features: ? ? ? ? ? first-in/first-out dual-port memory ? ? ? ? ? 2,048 x 9 organization (idt7203) ? ? ? ? ? 4,096 x 9 organization (idt7204) ? ? ? ? ? 8,192 x 9 organization (idt7205) ? ? ? ? ? 16,384 x 9 organization (idt7206) ? ? ? ? ? 32,768 x 9 organization (idt7207) ? ? ? ? ? 65,636 x 9 organization (idt7208) ? ? ? ? ? high-speed: 12ns access time ? ? ? ? ? low power consumption ? active: 660mw (max.) ? power-down: 44mw (max.) ? ? ? ? ? asynchronous and simultaneous read and write ? ? ? ? ? fully expandable in both word depth and width ? ? ? ? ? pin and functionally compatible with idt720x family ? ? ? ? ? status flags: empty, half-full, full ? ? ? ? ? retransmit capability ? ? ? ? ? high-performance cmos technology ? ? ? ? ? military product compliant to mil-std-883, class b ? ? ? ? ? standard military drawing for #5962-88669 (idt7203), 5962-89567 (idt7203), and 5962-89568 (idt7204) are listed on this function description: the idt7203/7204/7205/7206/7207/7208 are dual-port memory buffers with internal pointers that load and empty data on a first-in/first-out basis. the device uses full and empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. data is toggled in and out of the device through the use of the write ( w ) and read ( r ) pins. the device's 9-bit width provides a bit for a control or parity at the user?s option. it also features a retransmit ( rt ) capability that allows the read pointer to be reset to its initial position when rt is pulsed low. a half-full flag is available in the single device and width expansion modes. these fifos are fabricated using idt?s high-speed cmos technology. they are designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering and other applications. military grade product is manufactured in compliance with the latest revision of mil-std-883, class b. functional block diagram ? industrial temperature range (?40 c to +85 c) is available (plastic packages only) w write control read control r flag logic expansion logic xi write pointer ram array 2,048 x 9 4,096 x 9 8,192 x 9 16,384 x 9 32,768 x 9 65,536 x 9 read pointer data inputs reset logic three- state buffers data outputs ef ff xo / hf rs fl / rt 0 (d -d 8 ) 0 (q -q 8 ) 2661 drw01 ? ? ? ? ? green parts available, see ordering information
2 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 pin configurations symbol rating com'l & ind'l military unit v term terminal ?0.5 to +7.0 ?0.5 to +7.0 v voltage with respect to gnd t stg storage ?55 to + 125 ?65 to +155 c temperature i out dc output ?50 to +50 ?50 to +50 ma +current reference order device package type identifier code availability plastic dip p28-1 p all devices plastic thin dip p28-2 t p all except idt7207/7208 cerdip d28-1 d all except idt7208 thin cerdip d28-3 td only for idt7203/7204/7205 soic so28-3 so only for idt7204 reference order device package type identifier code availability plcc j32-1 j all devices lcc (1) l32-1 l all except idt7208 top view top view note: 1. this package is only available in the military temperature range. notes: 1. for rt / rs / xi input, v ih = 2.6v (commercial). for rt / rs / xi input, v ih = 2.6v (military). 2. 1.5v undershoots are allowed for 10ns once per cycle. 5 6 7 8 9 10 11 12 13 ff xi gnd 1 2 3 4 14 28 27 26 25 24 23 22 21 ef xo / hf vcc fl / rt rs 20 19 18 17 16 15 w d 4 q 7 r 2661 drw02a d 5 d 7 d 6 q 6 q 5 q 4 q 8 q 3 q 2 q 1 q 0 d 8 d 3 d 2 d 1 d 0 5 6 7 8 9 10 11 12 13 ff xi q 0 29 28 27 26 25 24 23 22 21 ef xo / hf d 6 nc fl / rt rs 14 15 16 17 18 19 20 4 3 2 1 32 31 30 index nc w nc vcc gnd nc r 2661 drw02b d 7 d 4 d 5 d 8 d 3 d 2 d 1 d 0 q 1 q 2 q 7 q 6 q 4 q 5 q 8 q 3 absolute maximum ratings note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v commercial/industrial/military gnd supply voltage 0 0 0 v v ih (1) input high voltage 2.0 ? ? v commercial/industrial v ih (1) input high voltage military 2.2 ? ? v v il (2) input low voltage ? ? 0.8 v commercial/industrial/military t a operating temperature commercial 0 ? 70 c t a operating temperature industrial ?40 ? 85 c t a operating temperature military ?55 ? 125 c
3 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 idt7203 (1) idt7203 idt7204 (1) idt7204 commercial and industrial military (3) t a = 12, 15, 20, 25, 35, 50 ns t a = 20, 30, 40 ns symbol parameter min. typ. max. min. typ. max. unit i li (6) input leakage current (any input) ?1 ? 1 ?1 ? 1 a i lo (7) output leakage current ?10 ? 10 ?10 ? 10 a v oh output logic ?1? voltage i oh = ?2ma 2.4 ? ? 2.4 ? ? v v ol output logic ?0? voltage i ol = 8ma ? ? 0.4 ? ? 0.4 v i cc1 (8,9,10) active power supply current ? ? 120 ? ? 150 ma i cc2 (8,10,11) standby current ( r = w = rs = fl / rt =v ih ) ??12? ?25ma i cc3 (8,10,12) power down current ? ? 2 ? ? 4 ma ac test conditions notes: 1. industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. 2. industrial temperature range product for 25ns speed grade only is available as a standard device. all other speed grades are available by special order. 3. military temperature range product for the 40ns is only available for 7203. 4. commercial temperature range product for the 12ns not available. 5. commercial temperature range product for the 12ns, 15ns and 50ns not available. idt7205 (2) idt7205 idt7206 (2,4) idt7206 idt7207 (2,4) idt7207 idt7208 (2,5) commercial and industrial military t a = 12, 15, 20, 25, 35, 50 ns t a = 20, 30 ns symbol parameter min. typ. max. min. typ. max. unit i li (6) input leakage current (any input) ?1 ? 1 ?1 ? 1 a i lo (7) output leakage current ?10 ? 10 ?10 ? 10 a v oh output logic ?1? voltage i oh = ?2ma 2.4 ? ? 2.4 ? ? v v ol output logic ?0? voltage i ol = 8ma ? ? 0.4 ? ? 0.4 v i cc1 (8,9,10) active power supply current ? ? 120 ? ? 150 ma i cc2 (8,10,11) standby current ( rs = fl / rt =v ih )??12??25ma i cc3 (8,10,12) power down current ? ? 8 ? ? 12 ma input pulse levels gnd to 3.0v input rise/fall times 5ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 1.1k ? 30pf* 680 ? 5v d.u.t. or equivalent circuit 2661 drw03 dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c; industrial: v cc = 5v 10%, t a = ?40 c to +85 c; military: v cc = 5v 10%, t a = ?55 c to +125 c) 6. measurements with 0.4 v in v cc . 7. r v ih , 0.4 v out v cc . 8. tested with outputs open (i out = 0). 9. r and w toggle at 20 mhz and data inputs switch at 10 mhz. 10. i cc measurements are made with outputs open. 11. all inputs = v cc - 0.2v or gnd + 0.2v, except r and w , which toggle at 20mhz. 12. all inputs = v cc - 0.2v or gnd + 0.2v, except r and w = v cc -0.2v. capacitance (1) (t a = +25 c, f = 1.0 mhz) notes: 1. this parameter is sampled and not 100% tested. 2. with output deselected. symbol parameter condition max. unit c in (1) input capacitance v in = 0v 10 pf c out (1,2) output capacitance v out = 0v 10 pf figure 1. output load *includes jig and scope capacitances.
4 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 commercial com'l & ind'l com'l & military commercial com'l & ind'l idt7203l12 idt7203l15 (2) idt7203l20 idt7208l20 idt7203l25 (2) idt7204l12 idt7204l15 (2) idt7204l20 idt7204l25 (2) idt7205l12 idt7205l15 idt7205l20 idt7205l25 (3) idt7206l15 idt7206l20 idt7206l25 (3) idt7207l15 idt7207l20 idt7207l25 (3) idt7208l25 (3) symbol parameters min. max. min. max. min. max. min. max. min. max. unit f s shift frequency ? 50 ? 40 ? 33.3 ? 33.3 ? 28.5 m h z t rc read cycle time 20 ? 25 ? 30 ? 30 ? 35 ? ns t a access time ? 12 ? 15 ? 20 ? 20 ? 25 ns t rr read recovery time 8 ? 10 ? 10 ? 10 ? 10 ? ns t rpw read pulse width (4) 12 ? 15 ? 20 ? 20 ? 25 ? ns t rlz read low to data bus low (5) 3?5 ?5?5?5?ns t wlz write high to data bus low-z (5,6) 3?5 ?5?5?5?ns t dv data valid from read high 5 ? 5 ? 5 ? 5 ? 5 ? ns t rhz read high to data bus high-z (5) ?12? 15?15?15?18ns t wc write cycle time 20 ? 25 ? 30 ? 30 ? 35 ? ns t wpw write pulse width (4) 12 ? 15 ? 20 ? 20 ? 25 ? ns t wr write recovery time 8 ? 10 ? 10 ? 10 ? 10 ? ns t ds data set-up time 9 ? 11 ? 12 ? 12 ? 15 ? ns t dh data hold time 0 ? 0 ? 0 ? 0 ? 0 ? ns t rsc reset cycle time 20 ? 25 ? 30 ? 30 ? 35 ? ns t rs reset pulse width (4) 12 ? 15 ? 20 ? 20 ? 25 ? ns t rss reset set-up time (5) 12 ? 15 ? 20 ? 20 ? 25 ? ns t rtr reset recovery time 8 ? 10 ? 10 ? 10 ? 10 ? ns t rtc retransmit cycle time 20 ? 25 ? 30 ? 30 ? 35 ? ns t rt retransmit pulse width (4) 12 ? 15 ? 20 ? 20 ? 25 ? ns t rts retransmit set-up time (5) 12 ? 15 ? 20 ? 20 ? 25 ? ns t rtr retransmit recovery time 8 ? 10 ? 10 ? 10 ? 10 ? ns t efl reset to ef low ?12? 25?30?30?35ns t hfh , t ffh reset to hf and ff high ? 17 ? 25 ? 30 ? 30 ? 35 ns t rtf retransmit low to flags valid ? 20 ? 25 ? 30 ? 30 ? 35 ns t ref read low to ef low ?12? 15?20?20?25ns t rff read high to ff high ? 14 ? 15 ? 20 ? 20 ? 25 ns t rpe read pulse width after ef high 12 ? 15 ? 20 ? 20 ? 25 ? ns t wef write high to ef high ? 12 ? 15 ? 20 ? 20 ? 25 ns t wff write low to ff low ?14? 15?20?20?25ns t whf write low to hf flag low ? 17 ? 25 ? 30 ? 30 ? 35 ns t rhf read high to hf flag high ? 17 ? 25 ? 30 ? 30 ? 35 ns t wpf write pulse width after ff high 12 ? 15 ? 20 ? 20 ? 25 ? ns t xol read/write low to xo low ?12? 15?20?20?25ns t xoh read/write high to xo high ? 12 ? 15 ? 20 ? 20 ? 25 ns t xi xi pulse width (4) 12 ? 15 ? 20 ? 20 ? 25 ? ns t xir xi recovery time 8 ? 10 ? 10 ? 10 ? 10 ? ns t xis xi set-up time 8 ? 10 ? 10 ? 10 ? 10 ? ns ac electrical characteristics (1) (commercial: v cc = 5v 10%, t a = 0 c to +70 c; industrial: v cc = 5v 10%, t a = ?40 c to +85 c; military: v cc = 5v 10%, t a = ?55 c to +125 c) notes: 1. timings referenced as in ac test conditions. 2. industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. 3. industrial temperature range product for 25ns speed grade only is available as a standard device. all other speed grades are available by special order. 4. pulse widths less than minimum are not allowed. 5. values guaranteed by design, not currently tested. 6. only applies to read data flow-through mode.
5 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 ac electrical characteristics (1) (continued) (commercial: v cc = 5v 10%, t a = 0 c to +70 c; industrial: v cc = 5v 10%, t a = ?40 c to +85 c; military: v cc = 5v 10%, t a = ?55 c to +125 c) notes: 1. timings referenced as in ac test conditions. 2. pulse widths less than minimum are not allowed. 3. values guaranteed by design, not currently tested. 4. only applies to read data flow-through mode. military commercial military commercial idt7203l30 idt7203l35 idt7203l40 idt7203l50 idt7204l30 idt7204l35 idt7204l50 idt7205l30 idt7205l35 idt7205l50 idt7206l30 idt7206l35 idt7206l50 idt7207l30 idt7207l35 idt7207l50 idt7208l35 symbol parameters min. max. min. max. min. max. min. max. unit f s shift frequency ? 25 ? 22.22 ? 20 ? 15 m h z t rc read cycle time 40 ? 45 ? 50 ? 65 ? ns t a access time ? 30 ? 35 ? 40 ? 50 ns t rr read recovery time 10 ? 10 ? 10 ? 15 ? ns t rpw read pulse width (2) 30 ? 35 ? 40 ? 50 ? ns t rlz read low to data bus low (3) 5? 5?5?10?ns t wlz write high to data bus low-z (3,4) 5 ? 10 ? 10 ? 15 ? ns t dv data valid from read high 5 ? 5 ? 5 ? 5 ? ns t rhz read high to data bus high-z (3) ?20 ?20?25?30ns t wc write cycle time 40 ? 45 ? 50 ? 65 ? ns t wpw write pulse width (2) 30 ? 35 ? 40 ? 50 ? ns t wr write recovery time 10 ? 10 ? 10 ? 15 ? ns t ds data set-up time 18 ? 18 ? 20 ? 30 ? ns t dh data hold time 0 ? 0 ? 0 ? 5 ? ns t rsc reset cycle time 40 ? 45 ? 50 ? 65 ? ns t rs reset pulse width (2) 30 ? 35 ? 40 ? 50 ? ns t rss reset set-up time (3) 30 ? 35 ? 40 ? 50 ? ns t rtr reset recovery time 10 ? 10 ? 10 ? 15 ? ns t rtc retransmit cycle time 40 ? 45 ? 50 ? 65 ? ns t rt retransmit pulse width (2) 30 ? 35 ? 40 ? 50 ? ns t rts retransmit set-up time (3) 30 ? 35 ? 40 ? 50 ? ns t rtr retransmit recovery time 10 ? 10 ? 10 ? 15 ? ns t efl reset to ef low ?40 ?45?50?65ns t hfh , t ffh reset to hf and ff high ? 40 ? 45 ? 50 ? 65 ns t rtf retransmit low to flags valid ? 40 ? 45 ? 50 ? 65 ns t ref read low to ef low ?30 ?30?35?45ns t rff read high to ff high ? 30 ? 30 ? 35 ? 45 ns t rpe read pulse width after ef high 30 ? 35 ? 40 ? 50 ? ns t wef write high to ef high ? 30 ? 30 ? 35 ? 45 ns t wff write low to ff low ?30 ?30?35?45ns t whf write low to hf flag low ? 40 ? 45 ? 50 ? 65 ns t rhf read high to hf flag high ? 40 ? 45 ? 50 ? 65 ns t wpf write pulse width after ff high 30 ? 35 ? 40 ? 50 ? ns t xol read/write low to xo low ?30 ?35?40?50ns t xoh read/write high to xo high ? 30 ? 35 ? 40 ? 50 ns t xi xi pulse width (2) 30 ? 35 ? 40 ? 50 ? ns t xir xi recovery time 10 ? 10 ? 10 ? 10 ? ns t xis xi set-up time 10 ? 15 ? 15 ? 15 ? ns
6 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 loaded (see operating modes). the single device mode is initiated by grounding the expansion in ( xi ). the idt7203/7204/7205/7206/7207/7208 can be made to retransmit data when the retransmit enable control ( rt ) input is pulsed low. a retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. the status of the flags will change depending on the relative locations of the read and write pointers. read enable ( r ) and write enable ( w ) must be in the high state during retransmit. this feature is useful when less than 2,048/ 4,096/8,192/16,384/32,768/65,536 writes are performed between resets. the retransmit feature is not compatible with the depth expansion mode. expansion in ( xi ) ? this input is a dual-purpose pin. expansion in ( xi ) is grounded to indicate an operation in the single device mode. expansion in ( xi ) is connected to expansion out ( xo ) of the previous device in the depth expansion or daisy-chain mode. outputs: full flag ( ff ) ? the full flag ( ff ) will go low, inhibiting further write operations, when the device is full. if the read pointer is not moved after reset ( rs ), the full flag ( ff ) will go low after 2,048/4,096/8,192/16,384/32,768/65,536 writes. empty flag ( ef ) ? the empty flag ( ef ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. expansion out/half-full flag ( xo / hf ) ? this is a dual-purpose output. in the single device mode, when expansion in ( xi ) is grounded, this output acts as an indication of a half-full memory. after half of the memory is filled, and at the falling edge of the next write operation, the half-full flag ( hf ) will be set to low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset by the rising edge of the read operation. in the depth expansion mode, expansion in ( xi ) is connected to expansion out ( xo ) of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse to the next device when the previous device reaches the last location of memory. there will be an xo pulse when the write pointer reaches the last location of memory, and an additional xo pulse when the read pointer reaches the last location of memory. data outputs (q 0 -q 8 ) ? q 0 -q 8 are data outputs for 9-bit wide data. these outputs are in a high-impedance condition whenever read ( r ) is in a high state. signal descriptions inputs: data in (d 0 ?d 8 ) ? data inputs for 9-bit wide data. controls: reset ( rs ) ? reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power-up before a write operation can take place. both the read enable ( r ) and write enable ( w ) inputs must be in the high state during the window shown in figure 2 (i.e. t rss before the rising edge of rs ) and should not change until t rsr after the rising edge of rs . write enable ( w ) ? a write cycle is initiated on the falling edge of this input if the full flag ( ff ) is not set. data set-up and hold times must be adhered- to, with respect to the rising edge of the write enable ( w ). data is stored in the ram array sequentially and independently of any on-going read operation. after half of the memory is filled, and at the falling edge of the next write operation, the half-full flag ( hf ) will be set to low, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. the half-full flag ( hf ) is then reset by the rising edge of the read operation. to prevent data overflow, the full flag ( ff ) will go low on the falling edge of the last write signal, which inhibits further write operations. upon the completion of a valid read operation, the full flag ( ff ) will go high after t rff , allowing a new valid write to begin. when the fifo is full, the internal write pointer is blocked from w , so external changes in w will not affect the fifo when it is full. read enable ( r ) ? a read cycle is initiated on the falling edge of the read enable ( r ), provided the empty flag ( ef ) is not set. the data is accessed on a first-in/first-out basis, independent of any ongoing write operations. after read enable ( r ) goes high, the data outputs (q 0 through q 8 ) will return to a high- impedance condition until the next read operation. when all the data has been read from the fifo, the empty flag ( ef ) will go low, allowing the ?final? read cycle but inhibiting further read operations, with the data outputs remaining in a high- impedance state. once a valid write operation has been accomplished, the empty flag ( ef ) will go high after t wef and a valid read can then begin. when the fifo is empty, the internal read pointer is blocked from r so external changes will not affect the fifo when it is empty. first load/retransmit ( fl / rt ) ? this is a dual-purpose input. in the depth expansion mode, this pin is grounded to indicate that it is the first device
7 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 figure 4. full flag timing from last write to first read note: 1. w and r = v ih around the rising edge of rs . figure 2. reset figure 3. asynchronous write and read operation w rs r ef hf , ff t rsc t rs t rss t rss t rsr t efl t hfh, t ffh 2661 drw04 r w d 0 -d 8 t rc t a t wr t ds data t dh t wpw t wc valid t rhz t dv t a t rr t rpw in valid data out valid data out data in valid 2661 drw05 q 0 -q 8 t rlz r w ff t rff t wff first read ignored write last write 2661 drw06
8 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 figure 5. empty flag timing from last read to first write note: 1. ef , ff and hf may change status during retransmit, but flags will be valid at t rtc . figure 7. minimum timing for an empty flag coincident read pulse. figure 8. minimum timing for a full flag coincident write pulse. w r ef t wef t ref first write ignored read last read data out valid t a 2661 drw07 t rtc t rt t rts rt w,r hf, ef, ff t rtr flag valid 2661 drw08 t rtf ef w r t rpe 2661 drw09 t wef ff r w t wpf 2661 drw10 t rff figure 6. retransmit
9 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 figure 9. half-full flag timing figure 10. expansion out figure 11. expansion in operating modes: care must be taken to assure that the appropriate flag is monitored by each system (i.e. ff is monitored on the device where w is used; ef is monitored on the device where r is used). for additional information on the idt7203/7204/ 7205/7206/7207, refer to tech note 8: operating fifos on full and empty boundary conditions and tech note 6: designing with fifos. single device mode a single idt7203/7204/7205/7206/7207/7208 may be used when the application requirements are for 2,048/4,096/8,192/16,384/32,768/65,536 words or less. these fifos are in a single device configuration when the expansion in ( xi ) control input is grounded (see figure 12). depth expansion these fifos can easily be adapted to applications when the require- ments are for greater than 2,048/4,096/8,192/16,384/32,768/65,536 words. figure 14 demonstrates depth expansion using three idt7203/7204/7205/ 7206/7207/7208s. any depth can be attained by adding additional idt7203/ 7204/7205/7206/7207/7208s. these devices operate in the depth expansion mode when the following conditions are met: 1. the first device must be designated by grounding the first load ( fl ) control input. 2. all other devices must have fl in the high state. 3. the expansion out ( xo ) pin of each device must be tied to the expansion in ( xi ) pin of the next device. see figure 14. 4. external logic is needed to generate a composite full flag ( ff ) and empty flag ( ef ). this requires the oring of all ef s and oring of all ff s (i.e. all must be set to generate the correct composite ff or ef ). see figure 14. 5. the retransmit ( rt ) function and half-full flag ( hf ) are not available in the depth expansion mode. for additional information on the idt7203/7204/7205/7206/7207, refer to tech note 9: cascading fifos or fifo modules. w r hf half-full or less more than half-full half-full or less t rhf t whf 2661 drw11 w r xo write to last physical location t xol t xoh read from last physical location 2661 drw12 t xoh t xol w r xi write to first physical location read from first physical location t xi t xir 2661 drw13 t xis t xis
10 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 idt 7203 7204 7205 7206 7207 7208 xi xi 9 18 9 write ( w ) full flag ( ff ) reset ( rs ) 99 18 hf hf data (d) in read ( r ) empty flag ( ef ) retransmit ( rt ) data (q) out idt 7203 7204 7205 7206 7207 7208 2661 drw15 usage modes: width expansion word width may be increased simply by connecting the corresponding input control signals of multiple devices. status flags ( ef , ff and hf ) can be detected from any one device. figure 13 demonstrates an 18-bit word width by using two idt7203/7204/7205/7206/7207/7208s. any word width can be attained by adding additional idt7203/7204/7205/7206/7207/7208s (figure 13). bidirectional operation applications which require data buffering between two systems (each system capable of read and write operations) can be achieved by pairing idt7203/7204/7205/7206/7207/7208s as shown in figure 16. both depth expansion and width expansion may be used in this mode. data flow-through two types of flow-through modes are permitted, a read flow-through and write flow-through mode. for the read flow-through mode (figure 17), the fifo permits a reading of a single word after writing one word of data into an empty fifo. the data is enabled on the bus in (t wef + t a ) ns after the rising edge of w , called the first write edge, and it remains on the bus until the r line is raised from low-to-high, after which the bus would go into a three-state mode after t rhz ns. the ef line would have a pulse showing temporary deassertion and then would be asserted. in the write flow-through mode (figure 18), the fifo permits the writing of a single word of data immediately after reading one word of data from a full fifo. the r line causes the ff to be deasserted but the w line being low causes it to be asserted again in anticipation of a new data word. on the rising edge of w , the new word is loaded in the fifo. the w line must be toggled when ff is not asserted to write new data in the fifo and to increment the write pointer. compound expansion the two expansion techniques described above can be applied together in a straightforward manner to achieve large fifo arrays (see figure 15). note: 1. flag detection is accomplished by monitoring the ff , ef and hf signals on either (any) device used in the width expansion configuration. do not connect any output signals together. figure 12. block diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 fifo used in single device mo de write ( w ) data in (d) full flag ( ff ) reset ( rs ) 9 read ( r ) 9 data out (q) empty flag ( ef ) retransmit ( rt ) expansion in ( xi ) ( hf ) idt 7203 7204 7205 7206 7207 7208 (half-full flag) 2661 drw14 figure 13. block diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 fifo memory used in widt h expansion mode
11 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 truth tables table 1 ? reset and retransmit single device configuration/width expansion mode note: 1. pointer will increment if flag is high. table 2 ? reset and first load depth expansion/compound expansion mode notes: 1. xi is connected to xo of previous device. see figure 14. 2. rs = reset input, fl/rt = first load/retransmit, ef = empty flag output, ff = full flag output, xi = expansion input, hf = half-full flag output figure 14. block diagram of 6,144 x 9, 12,288 x 9, 24,576 x 9, 49,152 x 9, 98,304 x 9, 196,608 x 9 fifo memory (depth expansio n) d w idt 7203 7204 7205 7206 7207 7208 ff ef fl xo rs full empty v cc r 9 9 99 xi 9 q ff ef fl xo xi ff ef fl xo xi idt 7203 7204 7205 7206 7207 7208 idt 7203 7204 7205 7206 7207 7208 2661 drw16 inputs internal status outputs mode rs fl / rt xi read pointer write pointer ef ff hf reset 0 x 0 location zero location zero 0 1 1 retransmit 1 0 0 location zero unchanged x x x read/write 1 1 0 increment (1) increment (1) xxx inputs internal status outputs mode rs fl / rt xi read pointer write pointer ef ff reset first device 0 0 (1) location zero location zero 0 1 reset all other devices 0 1 (1) location zero location zero 0 1 read/write 1 x (1) x x x x
12 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 notes: 1. for depth expansion block see section on depth expansion and figure 14. 2. for flag detection see section on width expansion and figure 13.. figure 16. bidirectional fifo operation idt 7201a r b ef b hf b w a ff a w b ff b system a system b q b 0-8 d b 0-8 q a 0-8 r a hf a ef a idt 7203 7204 7205 7206 7207 7208 d a 0-8 idt 7203 7204 7205 7206 7207 7208 2661 drw18 r , w , rs d 0 -d n d 0 -d 8 d 9 -d n d 9 -d 17 d 18 -d n d (n-8) -d n d (n-8) -d n q (n-8) -q n idt7203 idt7204 idt7205 idt7206 idt7207 idt7208 depth expansion block 2661 drw17 idt7203 idt7204 idt7205 idt7206 idt7207 idt7208 depth expansion block idt7203 idt7204 idt7205 idt7206 idt7207 idt7208 depth expansion block q (n-8) -q n q 9 -q 17 q 9 -q 17 q 0 -q 8 q 0 -q 8 figure 15. compound fifo expansion
13 commercial, industrial and military temperature ranges idt7203/7204/7205/7206/7207/7208 cmos asynchronous fifo 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 october 22, 2008 figure 17. read data flow-through mode w data r t rpe in ef data out t wlz t wef t ref data out valid 2661 drw19 t a figure 18. write data flow-through mode r data in w ff data out t dh t wff data in valid data out valid 2661 drw20 t rff t a t wpf t ds
14 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com ordering information notes: 1. industrial temperature range product for 15ns and 25ns speed grades are available as a standard device for idt7203/7204, and 25ns speed grade only is available as a standard device for idt7205/7206/7207/7208. all other speed grades are available by special order. 2. the lcc is only available in the military temperature range. 3. the idt7208 is only available in commercial speed grades of 20, 25 and 35 ns. 4. green parts are available. for specific speeds and packages contact your local sales office. 5. for "p", plastic dip, when ordering green package, the suffix is "pdg". x power xx speed x package x process/ temperature range blank commercial (0 c to +70 c) i (1) b industrial ( ? 40 to +85 c) military ( ? 55 c to +125 c) compliant to mil-std-883, class b p (5) tp d td j l (2) so plastic dip p28-1 plastic thin dip p28-2 (all except 7207/7208) cerdip d28-1 (all except 7208) thin cerdip d28-3 (only for 7203/7204/7205) plastic leaded chip carrier plcc j32-1 leadless chip carrier lcc l32-1 (all except 7208) small outline ic soic so28-3 (only 7204) 12 15 20 (3) 25 (3) 30 35 (3) 40 50 commercial 7203/04/05 only commercial and (industrial only 7203/04) commercial and military commercial and industrial military only commercial only military 7203 only commercial only xxxx device type 7203 ? 7204 ? 7205 ? 7206 ? 7207 ? 7208 ( 3) l low power access time (t a ) speed in nanoseconds 2661 drw21 2,048 x9 fifo 4,096 x 9 fifo 8,192 x 9 fifo 16,384 x 9 fifo 32,768 x 9 fifo 65,536 x 9 fifo x g green (4) data sheet history 05/10/2001 pgs. 2, 3, 4, 5, 11 and 14. 05/30/2001 pg. 2. 04/03/2006 pgs. 1 and 14. 10/22/2008 pg. 14.

▲Up To Search▲

Price & Availability of IDT7204L20DG

	To Download IDT7204L20DG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .